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http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11549Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kumar, Ajit | - |
| dc.date.accessioned | 2022-08-05T10:14:03Z | - |
| dc.date.available | 2022-08-05T10:14:03Z | - |
| dc.date.issued | 2021-06 | - |
| dc.identifier.govdoc | NB17061 | - |
| dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11549 | - |
| dc.language.iso | en | en_US |
| dc.publisher | IIT Kharagpur | en_US |
| dc.subject | Subthreshold model | en_US |
| dc.subject | Threshold voltage | en_US |
| dc.subject | Junctionless FETs | en_US |
| dc.subject | Double gate | en_US |
| dc.subject | Gate all around | en_US |
| dc.title | Subthreshold Modeling of Asymmetric Multi Gate Junctionless FETs with Scaled Equivalent Oxide Thickness | en_US |
| dc.type | Thesis | en_US |
| Appears in Collections: | Subthreshold Modeling of Asymmetric Multi Gate Junctionless FETs with Scaled Equivalent Oxide Thickness | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| NB17061_Abstract.pdf | 169.82 kB | Adobe PDF | View/Open | |
| NB17061_Thesis.pdf Restricted Access | 3.78 MB | Adobe PDF | View/Open Request a copy |
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