A Class of Pipelined Architectures to Realize High Speed Adaptive Equalizers

dc.contributor.author	Pervin, Suraiya
dc.date.accessioned	2017-07-14T05:20:03Z
dc.date.available	2017-07-14T05:20:03Z
dc.date.issued	2001-12-01
dc.identifier.govdoc	NB12731
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7831
dc.language.iso	en	en
dc.publisher	IIT, Kharagpur	en
dc.subject	Zero Latency	en
dc.subject	Pipelined Architecture	en
dc.subject	Karhmen Loeve Transform	en
dc.subject	Systolic Array	en
dc.subject	Adaptive Equalizer	en
dc.title	A Class of Pipelined Architectures to Realize High Speed Adaptive Equalizers	en
dc.type	Thesis	en