Synthesis of Low Power High Performance Mixed Cmos Vlsi Circuits

dc.contributor.author	Saipraveen, Kadiyala
dc.date.accessioned	2015-11-05T07:16:16Z
dc.date.available	2015-11-05T07:16:16Z
dc.date.issued	2015-01
dc.identifier.govdoc	NB15251
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5434
dc.language.iso	en	en
dc.publisher	IIT Kharagpur	en
dc.subject	Clock Gating	en
dc.subject	Sub Graph Matching	en
dc.subject	Cell-reordering	en
dc.subject	Mixed CMOS Synthesis	en
dc.subject	Unate Decomposition	en
dc.title	Synthesis of Low Power High Performance Mixed Cmos Vlsi Circuits	en
dc.type	Thesis	en