Algorithms and Architectures for Structured Low Density Parity Check Codes

dc.contributor.author	Shantharam, Kalipatnapu
dc.date.accessioned	2022-08-10T06:37:26Z
dc.date.available	2022-08-10T06:37:26Z
dc.date.issued	2020-02
dc.identifier.govdoc	NB17075
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11577
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Low Density Parity Check (LDPC) Codes	en_US
dc.subject	Binary compressed sensing	en_US
dc.subject	Low complexity VLSI Architecture	en_US
dc.subject	Bit flipping decoder	en_US
dc.subject	Non-Binary LDPC	en_US
dc.title	Algorithms and Architectures for Structured Low Density Parity Check Codes	en_US
dc.type	Thesis	en_US