Please use this identifier to cite or link to this item:
http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/8192
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Mandal, Chittaranjan A. | - |
dc.date.accessioned | 2017-08-23T09:38:17Z | - |
dc.date.available | 2017-08-23T09:38:17Z | - |
dc.date.issued | 1995-01-01 | - |
dc.identifier.govdoc | NB12062 | - |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/8192 | - |
dc.language.iso | en | en |
dc.publisher | IIT, Kharagpur | en |
dc.subject | Port Assignment | en |
dc.subject | Memory | en |
dc.subject | Interconnect Optimization | en |
dc.subject | Design Space Exploration | en |
dc.subject | Genetic Algorithms | en |
dc.subject | Complexity Analysis | en |
dc.subject | Algorithms | en |
dc.subject | Data Path Synthesis | en |
dc.subject | VLSI Design | en |
dc.title | Complexity Analysis and Algorithms for Data Path Synthesis | en |
dc.type | Thesis | en |
Appears in Collections: | Complexity Analysis and Algorithms for Data Path Synthesis |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
NB12062_Abstract.pdf | 205.31 kB | Adobe PDF | ![]() View/Open | |
NB12062_Thesis.pdf Restricted Access | 9.85 MB | Adobe PDF | View/Open Request a copy |
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