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  4. Synthesis of Testable VLSI Designs from High Level Specifications
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7712
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dc.contributor.authorMitra, Biswadip
dc.date.accessioned2017-07-10T09:28:08Z
dc.date.available2017-07-10T09:28:08Z
dc.date.issued1992-01-01
dc.identifier.govdocNB11773 ; NB11636
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/7712
dc.language.isoenen
dc.publisherIIT, Kharagpuren
dc.subjectVLSI Designsen
dc.subjectTechnology Mappingen
dc.subjectState Assignmenten
dc.subjectSynthesis for Testabilityen
dc.subjectSynthesisen
dc.titleSynthesis of Testable VLSI Designs from High Level Specificationsen
dc.typeThesisen
Appears in Collections:Synthesis of Testable VLSI Designs from High Level Specifications

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