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  4. An Integrated Approach to Partitioning – Placement – Wire Routing of Computer Logic Circuit
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/3026
Title: An Integrated Approach to Partitioning – Placement – Wire Routing of Computer Logic Circuit
Authors: Chaudhuri, P. Pal
Keywords: Computer logic graph
Simulation techniques
Hardware implementation
Algorithms
Semiconductor technology
Mother board
Redundant gatee
Chip carrier
Multilayer board
Logic circuit
Issue Date: Mar-1979
Publisher: IIT Kharagpur
Gov't Doc #: NB10843
URI: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/3026
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