The primary focus of this work is the development of a suitable low power robust LNA architecture for multi-standard wireless receiver applications. While designing LNA it has been observed that the passive components non-idealities worsen the performance of LNA drastically. Design challenges in order to improve the LNA performance and functionality become manifold in customer environment due to pad package parasitics etc. Therefore, a need for the development of a compact design approach taking care of the passive non-idealities and including pad-pin package parasitics has been strongly felt, which is the main driving force of this thesis work. The methodology developed in this work not only captures accurately the subthreshold or low-VT operation of LNA, but also suggests new topologies for gain improvement without appreciable changes in noise figure. How efficiently mutual coupling through inter-stage LNA can improve the gain has been explained in detail by theoretical analysis. This work also analytically establishes the most efficient topologies for concurrent dual-band LNA for multi-standard application. Keywords - Low noise amplifier, multi-standard LNA, low power, LNA stability, package parasitic aware design.
Thesis submitted for the award of the degree of Doctor of Philosophy (Ph.D.) in the Department of Electronics & Electrical Communication Engineering by Ashudeb Dutta under the supervision of Dr. T. K. Bhattacharyya and Prof. S. K. Lahiri Department of Electronics & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Kharagpur - 721 302, INDIA Thesis submitted in August 2008 and Revised version submitted on June 2009
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Issue Date | Title | Author(s) |
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2008 | CMOS Low-Noise Amplifier For Multi-Standard Wireless Receiver | Dutta, Ashudeb |
Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1