DSpace JSPUI

Analog High-Level Design Is Rapidly Becoming A Main Topic Of Interest In An Analog Design Automation Process Because Of Its Promise To Deliver Short Design Closure At Much Lesser Costs. This Has Motivated Us To Develop Methodologies Which Make Several Tasks Of The Analog High-Level Design Process Fast And Accurate. This Thesis Presents Optimization-Based Methodologies For The Task Of High-Level Performance Model Generation, Optimal Component-Level Topology Generation And High-Level Specification Translation. This Thesis First Presents A Non-Parametric Regression-Based Methodology For The Generation Of High-Level Performance Models For Analog Component Blocks. The Transistor Sizes Of The Circuit-Level Implementations Of The Component Blocks Along With A Set Of Geometry Constraints Applied Over Them Define The Sample Space. A Halton Sequence Generator Is Used As A Sampling Algorithm. Performance Data Are Generated By Simulating Each Sampled Circuit Configuration Through SPICE. Least Squares Support Vector Machine (LS-SVM) Is Used As A Regression Function. Optimal Values Of The Model Hyper Parameters Are Determined Through A Grid Search-Based Technique And A Genetic Algorithm (GA)-Based Technique. The Generalization Ability Of The Models Is Estimated Through A Hold-Out Method And A K-Fold Cross Validation Method. The Constructed Performance Models Have Been Used To Implement A Gabased Topology Sizing Process. The Advantages Of The Present Methodology Are That The Constructed Models Are Accurate With Respect To Real Circuit-Level Simulation Results, Fast To Evaluate And Have A Good Generalization Ability. In Addition, The Model Construction Time Is Low And The Construction Process Does Not Require Any Detailed Knowledge Of Circuit Design. The Entire Methodology Has Been Demonstrated With A Set Of Experimental Results. This Thesis Then Presents A Top-Down Methodology For The Generation Of An Optimal Functional And Component-Level Topology For Linear Analog Systems, Starting From A Transfer Function Model Of The System. The Given Transfer Functions Are Converted To State Space Model Which Acts As The Basis For Generation Of Topologies Of The System. The Topology Exploration Process Is Modeled As A State Space