Test Infrastructure Design for Power Aware System-on-Chip Testing Collection home page

Author: Chandan Giri
Supervisor: Dr. Santanu Chattopadhyay
Department of Electronics & Electrical Communication Engineering
Indian Institute Of Technology Kharagpur, India
January, 2008

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Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1
Issue DateTitleAuthor(s)
2008-01Test Infrastructure Design for Power Aware System-on-Chip TestingGiri, Chandan
Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1