DSpace at My University: Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process

Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process Collection home page

Author: Santunu Sarangi
Supervisor: Prof. T. K. Bhattacharyya
Electronics and Electrical Communication Engineering
Indian Institute of Technology Kharagpur, India
December, 2022

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Issue Date	Title	Author(s)
2022-12	Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process	Sarangi, Santunu

Collection's Items (Sorted by Submit Date in Descending order): 1 to 1 of 1

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Design and Development of Jitter Measurement Circuit for High-Speed SerDes System using 65 nm CMOS Process Collection home page

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