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  4. Concurrency Test Scenario Generation Using UML Transition Sequences
Please use this identifier to cite or link to this item: http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11355
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dc.contributor.authorShirole, Mahesh Raghunath-
dc.date.accessioned2022-07-12T10:28:50Z-
dc.date.available2022-07-12T10:28:50Z-
dc.date.issued2021-02-
dc.identifier.govdocNB16963-
dc.identifier.urihttp://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11355-
dc.language.isoenen_US
dc.publisherIIT Kharagpuren_US
dc.subjectUML transition sequencesen_US
dc.subjectActivity diagramen_US
dc.subjectSequence diagramen_US
dc.subjectConcurrency coverage criteriaen_US
dc.subjectInterleaving test scenario generationen_US
dc.titleConcurrency Test Scenario Generation Using UML Transition Sequencesen_US
dc.typeThesisen_US
Appears in Collections:Concurrency Test Scenario Generation Using UML Transition Sequences

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