Spur Reduction Architectures for Fractional Frequency Synthesizers

dc.contributor.author	Biswas, Debdut
dc.date.accessioned	2021-07-16T11:57:00Z
dc.date.available	2021-07-16T11:57:00Z
dc.date.issued	2020-05
dc.identifier.govdoc	NB16722
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9674
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Spur calculation	en_US
dc.subject	Control voltage approximation	en_US
dc.subject	Control voltage sampler	en_US
dc.subject	Phase correction	en_US
dc.subject	Multiphase fractional PLL	en_US
dc.title	Spur Reduction Architectures for Fractional Frequency Synthesizers	en_US
dc.type	Thesis	en_US