Design Intent Verification by Formal Property Coverage

dc.contributor.author	Basu, Prasenjit
dc.date.accessioned	2018-05-02T05:45:38Z
dc.date.available	2018-05-02T05:45:38Z
dc.date.issued	2006-06-15
dc.identifier.govdoc	NB13732; NB13454; NB13811
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/9135
dc.language.iso	en	en
dc.publisher	IIT, Kharagpur	en
dc.subject	Magellan	en
dc.subject	Electronic Design Automation	en
dc.subject	System Verilog Assertions	en
dc.subject	Pre-silicon Validation	en
dc.subject	Formal Property Verification	en
dc.title	Design Intent Verification by Formal Property Coverage	en
dc.type	Thesis	en