dc.contributor.author | Mandal, Chittaranjan A. | |
dc.date.accessioned | 2017-08-23T09:38:17Z | |
dc.date.available | 2017-08-23T09:38:17Z | |
dc.date.issued | 1995-01-01 | |
dc.identifier.govdoc | NB12062 | |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/8192 | |
dc.language.iso | en | en |
dc.publisher | IIT, Kharagpur | en |
dc.subject | Port Assignment | en |
dc.subject | Memory | en |
dc.subject | Interconnect Optimization | en |
dc.subject | Design Space Exploration | en |
dc.subject | Genetic Algorithms | en |
dc.subject | Complexity Analysis | en |
dc.subject | Algorithms | en |
dc.subject | Data Path Synthesis | en |
dc.subject | VLSI Design | en |
dc.title | Complexity Analysis and Algorithms for Data Path Synthesis | en |
dc.type | Thesis | en |