dc.contributor.author | Rao, C. V. Guru | |
dc.date.accessioned | 2017-08-21T09:15:22Z | |
dc.date.available | 2017-08-21T09:15:22Z | |
dc.date.issued | 2003-10-01 | |
dc.identifier.govdoc | NB13122 | |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/8136 | |
dc.language.iso | en | en |
dc.publisher | IIT, Kharagpur | en |
dc.subject | Design-For-Test | en |
dc.subject | Systematic Methodology | en |
dc.subject | High Fault Coverage | en |
dc.subject | Soc Designs | en |
dc.subject | System-Level | en |
dc.title | Design-for-Test Techniques for SOC Designs | en |
dc.type | Thesis | en |