dc.contributor.author | Chakraborty, Rupsa | |
dc.date.accessioned | 2010-07-07T11:07:05Z | |
dc.date.available | 2010-07-07T11:07:05Z | |
dc.date.issued | 2010 | |
dc.identifier.govdoc | NB14212 | |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/633 | |
dc.description.abstract | THE PRIMARY CHALLENGE during the modern integrated circuit development process lies in coping with the progressively shorter time-to-market of the chips. Modular design through design re-use in the System-on-Chip (SoC) technology though aids in reducing the design time, the process of testing and verification of such highly complex circuits turns out to be more challenging. | en |
dc.language.iso | en | en |
dc.publisher | IIT Kharagpur | en |
dc.subject | System-on-Chips | en |
dc.title | New Techniques in Testing and Timing Verification of System-on-Chips | en |
dc.type | Thesis | en |