Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis

dc.contributor.author	Hazra, Aritra
dc.date.accessioned	2015-11-17T05:44:04Z
dc.date.available	2015-11-17T05:44:04Z
dc.date.issued	2015-03
dc.identifier.govdoc	NB15171
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/5542
dc.language.iso	en	en
dc.publisher	IIT, Kharagpur	en
dc.subject	VLSI	en
dc.subject	Reliability	en
dc.subject	VLSI / Integrated Cir- cuits	en
dc.subject	Power Management	en
dc.subject	Formal Verification	en
dc.title	Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis	en
dc.type	Thesis	en