An Integrated Approach to Partitioning – Placement – Wire Routing of Computer Logic Circuit

dc.contributor.author	Chaudhuri, P. Pal
dc.date.accessioned	2014-10-16T06:38:36Z
dc.date.available	2014-10-16T06:38:36Z
dc.date.issued	1979-03
dc.identifier.govdoc	NB10843
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/3026
dc.language.iso	en	en
dc.publisher	IIT Kharagpur	en
dc.subject	Computer logic graph	en
dc.subject	Simulation techniques	en
dc.subject	Hardware implementation	en
dc.subject	Algorithms	en
dc.subject	Semiconductor technology	en
dc.subject	Mother board	en
dc.subject	Redundant gatee	en
dc.subject	Chip carrier	en
dc.subject	Multilayer board	en
dc.subject	Logic circuit	en
dc.title	An Integrated Approach to Partitioning – Placement – Wire Routing of Computer Logic Circuit	en
dc.type	Thesis	en