This Dissertation Presents A Philosophy Of Designing Sampled Data Architectures Where The Processing Is Carried Out In The Analog Domain Thereby Eliminating The Need For Analog-Todigital Converter Yet The Dsp Algorithms Can Be Applied Due To Discrete Time Nature Of The Data. The Elementary Operation Occurring In Almost All The Dsp Algorithms Is The Multiplyand- Accumulate (Mac) Operation. In This Work, Several Architectures Have Been Proposed For Computing Discrete Linear Transforms By Employing Various Methods Of Realizing The Mac Operation In Analog Domain On The Signal That Is Discretized In Time But Remains Unquantized In Its Level. The _Rst Architecture Presented Here Employs A Resistor String For Concurrently Multiplying The Signal With All Possible Coef_Cient Values By Utilizing The Principle Of Potential Divider And Then Subsequently Transfers Proportional Amount Of Charges Through Appropriate Switching Network To Various Switched Capacitor Integrators Whose Basic Design Has Been Modi_Ed To Realize Both Inverting And Non-Inverting Modes Of Operation By A Simple Clock Steering Mechanism, For Simultaneously Computing All The Required Output Points Of Discrete Cosine Transform (Dct), Discrete Hartley Transform (Dht) Or Any Other Such Transform. Another Architecture Is Also Presented For Computing Discrete Transforms, Where Capacitor Ratios Are Utilized To Realize Multiplication With Different Coef- _Cients And Is Expected To Have Higher Accuracy Than That Of Resistors. This Work Presents Yet Another Architecture Where Multiplication With Various Coef_Cients Can Be Realized In Current Domain By Means Of Scaling The Wl Ratio Of The Transistors. Finally, An Architecture Has Been Suggested Where Multiplication Is Achieved By Varying The Charging Time Of The Capacitors From Constant Current Sources, Thereby Shifting The Dependency Of Accuracy