| dc.contributor.author | SUBRAHMANYAM, J.S.R. | |
| dc.date.accessioned | 2014-09-15T06:27:47Z | |
| dc.date.available | 2014-09-15T06:27:47Z | |
| dc.date.issued | 1986-09 | |
| dc.identifier.govdoc | NB11244 | |
| dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/2650 | |
| dc.language.iso | en | en |
| dc.publisher | IIT Kharagpur | en |
| dc.subject | Dimensions | en |
| dc.subject | Circuit- level | en |
| dc.subject | Switching device | en |
| dc.subject | Diagnostic logic graph | en |
| dc.subject | Graph-theoritic model | en |
| dc.subject | Path-oriented algorithms | en |
| dc.subject | LSI circuits | en |
| dc.subject | Algebraic manipulations | en |
| dc.subject | Boolean e xpressions | en |
| dc.subject | Integrated Circuite | en |
| dc.subject | Digital systems | en |
| dc.subject | Circuit packaging | en |
| dc.title | Diagnostic Logic Graph For Analysis and Diagnosis of Digital Networks | en |
| dc.type | Thesis | en |