Design-For-Test Techniques for SOC Designs

dc.contributor.author	Rao, C. V. Guru
dc.date.accessioned	2026-07-01T10:20:26Z
dc.date.available	2026-07-01T10:20:26Z
dc.date.issued	2003-10
dc.identifier.govdoc	NB13123
dc.identifier.uri	http://127.0.0.1/xmlui/handle/123456789/17418
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Fault Model	en_US
dc.subject	Test Access Mechanism (TAM) Switch	en_US
dc.subject	Computer-Aided-Test (CAT) Tool	en_US
dc.title	Design-For-Test Techniques for SOC Designs	en_US
dc.type	Thesis	en_US