A Machine Learning Approach for Network-on-Chip Architecture Design

dc.contributor.author	Sambangi, Ramesh
dc.date.accessioned	2024-08-05T09:44:28Z
dc.date.available	2024-08-05T09:44:28Z
dc.date.issued	2024-02
dc.identifier.govdoc	NB18156
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/14963
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Network-On-Chip(Noc)	en_US
dc.subject	Noc Analytical Model	en_US
dc.subject	Application Mapping	en_US
dc.subject	Machine Learning	en_US
dc.subject	Message Passing Neural Network (MPNN)	en_US
dc.title	A Machine Learning Approach for Network-on-Chip Architecture Design	en_US
dc.type	Thesis	en_US