Low Power Logic Optimization and Synthesis

dc.contributor.author	Chaudhury, Saurabuh
dc.date.accessioned	2024-04-24T10:18:29Z
dc.date.available	2024-04-24T10:18:29Z
dc.date.issued	2009
dc.identifier.govdoc	NB13905
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/13338
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	Circuits	en_US
dc.subject	Power Optimization	en_US
dc.subject	CMOS VLSI Circuits	en_US
dc.subject	Low Power Dissipation	en_US
dc.title	Low Power Logic Optimization and Synthesis	en_US
dc.type	Thesis	en_US