dc.contributor.author | V, Rajesh | |
dc.date.accessioned | 2023-02-15T05:16:54Z | |
dc.date.available | 2023-02-15T05:16:54Z | |
dc.date.issued | 2022-06 | |
dc.identifier.govdoc | NB17467 | |
dc.identifier.uri | http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/12338 | |
dc.language.iso | en | en_US |
dc.publisher | IIT Kharagpur | en_US |
dc.subject | Multilevel Network | en_US |
dc.subject | Half-Bridge Level Doubling Network | en_US |
dc.subject | Full-Bridge Level Doubling Network | en_US |
dc.subject | Cascaded H-bridge | en_US |
dc.subject | Binary Asymmetric Ratio | en_US |
dc.title | Investigations on Multilevel Inverters with Single DC Source | en_US |
dc.type | Thesis | en_US |