Concurrency Test Scenario Generation Using UML Transition Sequences

dc.contributor.author	Shirole, Mahesh Raghunath
dc.date.accessioned	2022-07-12T10:28:50Z
dc.date.available	2022-07-12T10:28:50Z
dc.date.issued	2021-02
dc.identifier.govdoc	NB16963
dc.identifier.uri	http://www.idr.iitkgp.ac.in/xmlui/handle/123456789/11355
dc.language.iso	en	en_US
dc.publisher	IIT Kharagpur	en_US
dc.subject	UML transition sequences	en_US
dc.subject	Activity diagram	en_US
dc.subject	Sequence diagram	en_US
dc.subject	Concurrency coverage criteria	en_US
dc.subject	Interleaving test scenario generation	en_US
dc.title	Concurrency Test Scenario Generation Using UML Transition Sequences	en_US
dc.type	Thesis	en_US