New Techniques in Testing and Timing Verification of System-on-Chips http://127.0.0.1/xmlui/handle/123456789/632 Thu, 16 Apr 2026 21:41:44 GMT 2026-04-16T21:41:44Z New Techniques in Testing and Timing Verification of System-on-Chips http://127.0.0.1/xmlui/handle/123456789/633 New Techniques in Testing and Timing Verification of System-on-Chips Chakraborty, Rupsa THE PRIMARY CHALLENGE during the modern integrated circuit development process lies in coping with the progressively shorter time-to-market of the chips. Modular design through design re-use in the System-on-Chip (SoC) technology though aids in reducing the design time, the process of testing and verification of such highly complex circuits turns out to be more challenging. Fri, 01 Jan 2010 00:00:00 GMT http://127.0.0.1/xmlui/handle/123456789/633 2010-01-01T00:00:00Z