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<title>Genetic Algorithm based Logic Optimization and Synthesis Techniques with Area-Power Trade-offs</title>
<link>http://127.0.0.1/xmlui/handle/123456789/531</link>
<description/>
<pubDate>Fri, 17 Apr 2026 16:11:01 GMT</pubDate>
<dc:date>2026-04-17T16:11:01Z</dc:date>
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<title>Genetic Algorithm based Logic Optimization and Synthesis Techniques with Area-Power Trade-offs</title>
<link>http://127.0.0.1/xmlui/handle/123456789/532</link>
<description>Genetic Algorithm based Logic Optimization and Synthesis Techniques with Area-Power Trade-offs
Pradhan, Sambhu Nath
In recent times, power consumption has been recognized as an important issue in&#13;
implementing battery-operated portable devices. Power consumption of individual&#13;
blocks of VLSI circuit is reaching the limits of what can be dealt with by economic&#13;
packaging technologies, resulting in the reduction of chip reliability. As a result,&#13;
power consumption is being addressed in all levels of VLSI design hierarchy.&#13;
Obviously, the saving will be higher if power issues are taken care of early in the&#13;
design cycle. This has motivated us to consider power issue at the logic level. Though&#13;
dynamic power is still the major source of power consumption, aggressive technology&#13;
scaling to get the required performance with reduced production cost has the side&#13;
effect of increasing the transistor leakage current. Due to the exponential nature of&#13;
leakage current in the subthreshold regime operation of transistors, leakage current&#13;
can no longer be ignored. In this thesis we have addressed both the dynamic and&#13;
leakage power consumption of the circuit.
</description>
<pubDate>Fri, 01 Jan 2010 00:00:00 GMT</pubDate>
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<dc:date>2010-01-01T00:00:00Z</dc:date>
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