Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits http://127.0.0.1/xmlui/handle/123456789/2078 Thu, 16 Apr 2026 16:16:44 GMT 2026-04-16T16:16:44Z Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits http://127.0.0.1/xmlui/handle/123456789/2079 Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits Mitra, Srobona Sat, 01 Jun 2013 00:00:00 GMT http://127.0.0.1/xmlui/handle/123456789/2079 2013-06-01T00:00:00Z