New Techniques in Testing and Timing Verification of System-on-Chips http://127.0.0.1/xmlui/handle/123456789/632 2026-04-17T02:35:52Z New Techniques in Testing and Timing Verification of System-on-Chips http://127.0.0.1/xmlui/handle/123456789/633 New Techniques in Testing and Timing Verification of System-on-Chips Chakraborty, Rupsa THE PRIMARY CHALLENGE during the modern integrated circuit development process lies in coping with the progressively shorter time-to-market of the chips. Modular design through design re-use in the System-on-Chip (SoC) technology though aids in reducing the design time, the process of testing and verification of such highly complex circuits turns out to be more challenging. 2010-01-01T00:00:00Z