Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures

Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures http://127.0.0.1/xmlui/handle/123456789/9985 2026-04-18T03:10:07Z 2026-04-18T03:10:07Z Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures Roy, Rabisankar http://127.0.0.1/xmlui/handle/123456789/9986 2021-10-01T12:49:07Z 2020-11-01T00:00:00Z

Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures Roy, Rabisankar

2020-11-01T00:00:00Z