VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer http://127.0.0.1/xmlui/handle/123456789/1740 2026-04-18T00:12:05Z 2026-04-18T00:12:05Z VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer Karim, Shaikh Montajul http://127.0.0.1/xmlui/handle/123456789/1741 2015-06-01T12:28:58Z 2012-06-01T00:00:00Z VLSI Architectures for High Throughput Turbo Decoder and Reduced Complexity Turbo Equalizer Karim, Shaikh Montajul 2012-06-01T00:00:00Z